The present invention relates generally to integrated circuit differential amplifiers having high speed common mode feedback and also having programmable input offset trim capability, and more particularly to improvements which result in substantially reduced circuit complexity and substantially reduced noise levels.
In the prior art, there are several ways to accomplish input offset compensation, for example by trimming or calibrating load devices of the input stage or by injecting an offset compensation current into the circuit nodes between drains of the input transistors and their corresponding load devices. These input offset compensation techniques require an additional differential input transistor pair and associated tail current source and also require a trim voltage generator circuit, and are characterized by undesirably high noise levels and undesirably high circuit complexity.
“Prior Art” FIG. 1 shows a “conceptual” diagram of a differential amplifier 1 including an input stage 7 which includes input transistor pair 2, associated load devices 4, and a current source 7. Control electrodes of the input transistors in block 2 receive input signals Vin+ and Vin−. Current source 3 provides tail current for the common sources (or common emitters) of the input transistors in block 2. Block 4 includes load devices (e.g., load resistors or current sources) which are connected to drains (or collectors) of the input transistors in block 2. A common mode feedback circuit 6 is coupled to input stage 7 by means of any one of the circuit paths labeled Path A, Path B, or Path C to adjust corresponding common mode feedback points. Offset trim circuit 5 is coupled to input stage 7 by either Path D or Path E. The prior art techniques indicated in FIG. 1 also can be used in “ultra low voltage” differential amplifier designs which do not include tail current source 3. Various implementations of the individual blocks in FIG. 1 are known in the prior art.
The common mode feedback using Path A can be used to control tail current source 3 dynamically to adjust the common mode voltage level that occurs on the conductors connected between input transistor pair 2 and load devices 4. Alternatively, common mode feedback Path B directly adjusts or modulates the impedance of the load circuit in block 4 in order to adjust the common mode voltage level on the conductors connected between the individual load devices in block 4 and the drains (or collectors) of the input transistors in block 2. Alternatively, common mode feedback Path C can be used to adjust the common mode voltage level on the conductors connected between the individual load devices in block 4 and the corresponding input transistors in block 2 by injecting a common mode feedback current directly into those same conductors.
Input offset trim circuit 5 can use Path D in FIG. 1 to modulate the differential impedance of load devices 4 by injecting a constant differential current into the conductors connected between the load devices in block 4 and the drains (or collectors) of the corresponding input transistors in block 2.
Referring to “Prior Art” FIG. 2, offset trim generator circuit 5 of FIG. 1 receives a reference voltage VREF that is applied to the (+) input of a buffer amplifier 20. The output of buffer amplifier 20 is connected by conductor 19 to its (−) input and also to one terminal of a resistor 18, the other terminal of which is connected to the input of a current mirror 21. The output of current mirror 21 flows through an adjustable-resistance or tappable-resistance circuit 17A,B which is connected between VDD and the output of current mirror 21. An upper trim voltage VTRIM+ is produced on a tap point of adjustable-resistance circuit 17A,B, and a lower trim voltage VTRIM− is produced on another tap point of adjustable-resistance circuit 17A,B, or alternatively, on the output conductor 19 of buffer amplifier 20. Trim voltages VTRIM+ and VTRIM− can be used along Path E in FIG. 1, or they can be applied to the inputs of a buffer circuit (not shown) in Path D, in which case the outputs of the buffer circuit can be applied to the nodes between input transistor pair 2 and load devices 4.
Common mode feedback circuit 6 of FIG. 1 can be implemented in various ways, for example as indicated in the article “Fully Differential Operational Amplifiers with Accurate Output Balancing” by M. Banu, J. Khoury, and Y. Tsividis, IEEE Journal of Solid-State Circuits, Volume 23, Number 6, December 1988, pp. 1410-1414. This article discloses several known common mode feedback circuits for differential amplifiers.
The prior art differential amplifiers having both high speed common mode feedback and programmable input offset trim capability require undesirably complex circuitry and an undesirably large amount of integrated circuit chip area, and are characterized by undesirably high noise levels associated with the connections of the common mode feedback circuitry and offset trim generators to the amplifier input stage and by undesirably high power consumption.
Thus, there is an unmet need in the prior art for a differential amplifier having both high speed common mode feedback and programmable input offset trim capability and which has less complex circuitry than the closest prior art.
There also is an unmet need in the prior art for a differential amplifier having both high speed common mode feedback and programmable input offset trim capability and which has lower noise than the closest prior art.
There also is an unmet need in the prior art for a differential amplifier having both high speed common mode feedback and programmable input offset trim capability and which has substantially less complex circuitry and substantially lower noise then the closest prior art.
There also is an unmet need in the prior art for a differential amplifier having both high speed common mode feedback and programmable input offset trim capability and which has lower power dissipation than the closest prior art.
There also is an unmet need in the prior art for a differential amplifier having both high speed common mode feedback and programmable input offset trim capability and which requires less integrated circuit chip area than the closest prior art.